Figure 6 shows an astable circuit based on a NOT logic gate - AQA - A-Level Physics - Question 4 - 2018 - Paper 8

When drawing the output voltage waveform, ensure it is a square wave with the following characteristics:

1. The output switches between 0 V and $V_s$.
2. The frequency of the output matches the calculated PRF, with appropriate amplitude and timing reflecting the thresholds UST and LST.

To modify the circuit for a frequency 4 times that of the original, we set the new PRF:

$PRF_{new} = 4 \times 14 \text{ kHz} = 56 \text{ kHz}$

Using the PRF formula again:

$56 \text{ kHz} = \frac{1}{1.4 (R + R_{new}) C}$

Where $R_{new}$ is the added resistor. From the original configuration with $R = 5.1 \text{ kΩ}$:

Solving for $R_{new}$, we find the total resistance and the value of $R_{new}$ needed to achieve this frequency.

To obtain a frequency of 5 kHz with a 75% duty cycle means:

1. The period $T = \frac{1}{5 \text{ kHz}} = 0.2 \text{ ms}$.
2. Time for high state ($T_H = 0.75 \times T$) and low state ($T_L = 0.25 \times T$).

Using the charging and discharging formulas:

$t_C = 0.7 \times (R_1 + R_2) \times 10 \times 10^{-9} \text{ s}$ $t_D = 0.7 \times R_2 \times 10 \times 10^{-9} \text{ s}$

Set up equations based on the calculated times to determine $R_1$ and $R_2$, ensuring they meet the total resistance required for the circuit.

The wave pattern should resemble a square wave with:

1. An amplitude of 5 V during the charging stage.
2. Dropping to 0 V during the discharging period.
3. Period of $0.2 ms$ with a clear representation of the duty cycle.