4.1 Name TWO methods to display information in digital systems - NSC Electrical Technology Digital - Question 4 - 2021 - Paper 1

A common anode in a seven-segment LED display refers to a configuration where all the anodes of the LED segments are connected to a positive voltage. In this setup, the segments illuminate when their respective cathodes are grounded. This arrangement allows for easier control of the display by activating the segments by connecting them to ground while keeping the common anode at a positive potential.

Transistor coupling in LED seven-segment displays is used to control the current that flows through the segments. In the circuit represented in FIGURE 4.3, the transistor acts as a switch, allowing for the modulation of the LED segments by controlling the voltage applied to them. When the base of the transistor is energized, it conducts, allowing current to flow through the anode to illuminate the respective LED.

Polarisation of light refers to the orientation of light waves in a specific direction. In Liquid Crystal Displays (LCDs), polarised light is utilized to control visibility. When light passes through a polarizing filter, only waves aligned with that filter can pass. In an LCD, the liquid crystals can twist light's polarization based on the voltage applied, selectively allowing light to pass through a second polarizing filter, thus forming images or text.

The circuit in FIGURE 4.5 is identified as a decoder. It takes binary input signals and activates specific outputs based on the input combinations to decode the information.

The truth table for the outputs based on the combinations of inputs is as follows:

The logic circuit of a full adder can be represented with the following components:

• Inputs: A, B, Cin (carry-in)
• Outputs: Sum, Cout (carry-out)

Circuit Design:

1. Use two exclusive OR (XOR) gates to calculate the sum:
   • First XOR gate takes inputs A and B.
   • Second XOR gate takes the output of the first XOR gate and Cin.
2. For the carry-out (Cout):
   • Use two AND gates and one OR gate:
     • First AND gate takes inputs A and B.
     • Second AND gate takes inputs of the output from the first XOR gate and Cin.
     • The outputs of both AND gates are fed into the OR gate to produce Cout.

To complete the output waveforms for the clocked RS flip-flop in FIGURE 4.7:

• Trace the output based on the state changes of inputs S (Set) and R (Reset) with respect to the CLK (Clock) signal.
• S and R will determine Q and Q' (complement output), showing transitions may include:

1. When S = 1 and R = 0, Q goes high (1).
2. When S = 0 and R = 1, Q goes low (0).
3. The combination S = 0 and R = 0 will keep Q unchanged.
4. The state S = 1 and R = 1 is typically forbidden because it can lead to an indeterminate state.

The truth table for the clocked J-K flip-flop in FIGURE 4.8 is as follows:

A three-bit parallel adder consists of:

• Inputs: A2 A1 A0 (three bits from the first number) and B2 B1 B0 (three bits from the second number).
• Outputs: S2 S1 S0 (sum outputs) and Cout (carry out).

Circuit Design:

1. Sum Outputs: Each bit can be computed using full adders:
   • S0 = A0 XOR B0 XOR Cin
   • S1 = A1 XOR B1 XOR Cout0 (Cout from S0)
   • S2 = A2 XOR B2 XOR Cout1 (Cout from S1)
2. Carry Outputs: These propagate through:
   • Cout0 = (A0 AND B0) OR (Cin AND (A0 XOR B0))
   • Cout1 = (A1 AND B1) OR (Cout0 AND (A1 XOR B1))
   • Cout2 = (A2 AND B2) OR (Cout1 AND (A2 XOR B2))

Two types of counters commonly used in digital electronics are:

1. Asynchronous (Ripple) Counter: Counts in a ripple effect, as the output of one flip-flop serves as the clock input to the next.
2. Synchronous Counter: All flip-flops are driven by the same clock signal, allowing for faster and more predictable counting.

The primary difference between combinational and sequential logic circuits lies in their building elements:

• Combinational Logic Circuits: Use logic gates (AND, OR, NOT) and their output depends only on the present input values.
• Sequential Logic Circuits: Utilize memory elements like flip-flops and are dependent on both current inputs and past history (previous states), making them suitable for memory, timing, and control applications.

The counter in FIGURE 4.12 is identified as a three-bit synchronous down counter. It counts down from a predefined maximum value.

The truth table for the three-bit synchronous down counter is as follows:

Two types of shift registers used in digital circuits are:

1. Parallel-in: Serial-out (PISO) Shift Register: Allows parallel input of data and outputs it serially.
2. Serial-in: Parallel-out (SIPO) Shift Register: Accepts data serially and outputs it in parallel format.

In the block diagram of the serial-in: serial-out shift register (FIGURE 4.14):

• A: Serial Data Input
• B: Clock Input

The operation of the serial-in: serial-out shift register involves loading data bits one at a time into the register. Data enters serially through input A, with each bit shifted in on the clock pulse B. This process allows multiple bits to be stored sequentially, and upon further clock pulses, the bits can be shifted out in the same serial manner, one bit at a time.